ECCN 3E004
NSATTechnology required for the slicing, grinding and polishing of 300 mm diameter silicon wafers to achieve a 'Site Front least sQuares Range' ('SFQR') less than or equal to 20 nm at any site of 26 mm x 8 mm on the front surface of the wafer and an edge exclusion less than or equal to 2 mm.
What This ECCN Covers
ECCN 3E004 controls "technology" required for the slicing, grinding, and polishing of 300 mm diameter (and related) semiconductor wafers, as defined in the entry. The process know-how behind advanced wafer preparation is controlled for National Security and Anti-Terrorism reasons, including intangible transfers and "deemed exports."
Who needs to check this?
Wafer-preparation engineers and equipment suppliers, and firms transferring slicing/grinding/polishing process technology across borders or to foreign nationals.
Compliance tip
Control is specific to the wafer-processing technology the entry describes — map your know-how to that scope. Intangible transfers (process specs, training, foreign-national access as "deemed exports") require authorization analysis; verify the NS and AT Country Chart columns.
Control Reasons
Items controlled for national security reasons under multilateral export control regimes.
Items controlled for anti-terrorism reasons. Most items on the CCL have AT controls.
Disclaimer
This information is for reference only. For official classifications, consult BIS or a qualified export control professional.