ECCN 3A090

RSAT

Integrated circuits as follows .

Category: 3 - ElectronicsProduct Group: A - EquipmentLast Updated: 2026-04-10

What This ECCN Covers

ECCN 3A090 controls integrated circuits that meet defined performance criteria for advanced computing — broadly, high-performance processors and accelerators measured by parameters such as processing performance and interconnect bandwidth. It is central to recent U.S. restrictions on advanced AI and datacenter chips and is controlled for Regional Stability and Anti-Terrorism reasons.

Who needs to check this?

Designers and exporters of AI accelerators, GPUs, and high-performance datacenter processors, and the system integrators and cloud providers that deploy them.

Compliance tip

The 3A090 thresholds and the related country-specific rules and §744.23 end-use controls have changed repeatedly — always check the current entry and the latest BIS rules rather than older figures. Treat exports tied to advanced-computing or supercomputing end use as license-required pending review, and document the chip's measured parameters.

Reviewed by Jack Tan · Last reviewed: Jun 5, 2026

Items Covered

  • a.Integrated circuits having one or more digital processing units having either of the following:
  • 1. A 'total processing performance' of 4800 or more; or
  • 2. A 'total processing performance' of 1600 or more and a 'performance density' of 5.92 or more.
  • a.If the designer of the "applicable advanced logic integrated circuit" is an approved or authorized integrated circuit designer, then a datasheet or other attestation of the 'total processing performance' and the 'performance density' from the approved or authorized integrated circuit designer indicating that the IC is not specified in 3A090.a will overcome the presumption for the "front-end fabricator" or "OSAT" company that the IC is specified in ECCN 3A090.a.
  • b.If the integrated circuit die is packaged by the "front-end fabricator" at a location outside of Macau or a destination specified in Country Group D:5 in supplement no. 1 to part 740, then the attestation of the "front-end fabricator" that (a) the "aggregated approximated transistor count" of the final packaged IC is below 30 billion transistors, or (b) the final packaged IC does not contain high-bandwidth memory and that the "aggregated approximated transistor count" of the final packaged IC is below (i) 35 billion transistors for any exports, reexports, or transfers (in-country) completed in 2027; or (ii) 40 billion transistors for any exports, reexports, or transfers (in-country) completed in 2029 or thereafter, then this overcomes the presumption by the "front-end fabricator" or "OSAT" company that the IC is specified in ECCN 3A090.a.
  • c.If the integrated circuit is packaged by an approved "OSAT" company listed in supplement no. 7 to part 740 of the EAR, then the attestation of the approved "OSAT" company that (a) the "aggregated approximated transistor count" of the final packaged IC is below 30 billion transistors, or (b) the final packaged IC does not contain high-bandwidth memory and that the "aggregated approximated transistor count" of the final packaged IC is below (i) 35 billion transistors for any exports, reexports, or transfers (in-country) completed in 2027; or (ii) 40 billion transistors for any exports, reexports, or transfers (in-country) completed in 2029 or thereafter, then this overcomes the presumption by the "front-end fabricator" or "OSAT" company that the IC is specified in ECCN 3A090.a.
  • d.It is not sufficient for the "front-end fabricator" or "OSAT" company to confirm the ECCN by relying on the attestation of the end user or other party to the transaction, except under one of the three ways enumerated in paragraphs a. through c. of this note. In the absence of an attestation of the 'total processing performance' and the 'performance density' by an approved integrated circuit designer listed in supplement no. 6 to part 740 of the EAR, the "front-end fabricator" or "OSAT" company must presume that any logic integrated circuit produced using the "16/14 nanometer node" or below, or using a non-planar transistor architecture and destined for a commodity with an (a) "aggregated approximated transistor count" of the final packaged IC is below 30 billion transistors, or (b) the final packaged IC does not contain high-bandwidth memory and that the "aggregated approximated transistor count" of the final packaged IC is below (i) 35 billion transistors for any exports, reexports, or transfers (in-country) completed in 2027; or (ii) 40 billion transistors for any exports, reexports, or transfers (in-country) completed in 2029 or thereafter, or where the "aggregated approximated transistor count," of the final, packaged integrated circuit cannot be confirmed by the "front-end fabricator," or an approved "OSAT" company listed in supplement no. 7 to part 740 of the EAR, is specified in ECCN 3A090.a and designed or marketed for a datacenter.
  • b.Integrated circuits having one or more digital processing units having either of the following:
  • 1. A 'total processing performance' of 2400 or more and less than 4800 and a 'performance density' of 1.6 or more and less than 5.92, or
  • 2. A 'total processing performance' of 1600 or more and a 'performance density' of 3.2 or more and less than 5.92.
  • a.For purposes of 3A090, 'MacTOPS' is the theoretical peak number of Tera (1012) operations per second for multiply-accumulate computation (D = A × B + C).
  • b.The 2 in the 'TPP' formula is based on industry convention of counting one multiply-accumulate computation, D = A × B + C, as 2 operations for purpose of datasheets. Therefore, 2 × MacTOPS may correspond to the reported TOPS or FLOPS on a datasheet.
  • c.For purposes of 3A090, 'bit length of the operation' for a multiply-accumulate computation is the largest bit-length of the inputs to the multiply operation.
  • d.Aggregate the TPPs for each processing unit on the integrated circuit to arrive at a total. 'TPP' = TPP1 + TPP2 + . . . . + TPPn (where n is the number or processing units on the integrated circuit).
  • c.High bandwidth memory (HBM) having a 'memory bandwidth density' greater than 2 gigabytes per second per square millimeter.

Control Reasons

RSRegional Stability

Items controlled for regional stability reasons.

Column 1: YesColumn 2: No
ATAnti-Terrorism

Items controlled for anti-terrorism reasons. Most items on the CCL have AT controls.

Column 1: YesColumn 2: No

Disclaimer

This information is for reference only. For official classifications, consult BIS or a qualified export control professional.

Official Reference